1. Field of the Invention
The present invention relates to a color display device using a self-emissive element, such as an electroluminescence (EL) element, and a thin film transistor (TFT), and a method for designing a display device.
2. Description of the Related Art
There is today active development of flat panel display devices with reduced thickness and low power consumption as potential replacements for CRTs. One well-known type of flat panel display device is a liquid crystal display (LCD). In recent years, research has also being directed to development of an EL display device using self-emissive EL elements. In one known method for achieving color display in such flat panel display devices, self-emissive elements such as those used in an EL display device, which are composed of different materials for emitting the respective lights of R, G, and B, may be provided in corresponding pixel regions, so as to produce a full color display using a combination of light from the plurality of pixel regions.
In an EL element, and particularly referring to an organic EL element which employs an organic compound as the emissive material, the lifetime of the organic layer of the element very greatly influences the usable life of the entire color display device. The life of an organic layer differs for each emissive material. Accordingly, when using different materials for the respective emitted colors, achieving uniform EL material life for the respective color components leads to attaining a longer working life for display itself.
One method for attaining longer device life is to vary the size of the emissive region (region in which light is visible) in accordance with the characteristic of the EL material for each of the color components. Because an EL element life depends on the density of current that is made to flow in the element, the life can be effectively extended by minimizing the current density. Accordingly, for a short-life EL element, a desired luminance level may be achieved at a low current density by maximizing the element area.
FIG. 1A is a schematic plan view showing a widely used configuration of an active matrix type EL display device, which includes a thin film transistor in each pixel region for individually controlling light emission from each EL element. Gate signal lines 151 are formed along the horizontal direction, while drain (data) signal lines 152 and drive power lines 153 are formed along the vertical direction. Each pixel region is arranged generally in a region surrounded by gate signal lines 151, a drain signal line 152, and a drive power line 153. In a typical configuration, each pixel region includes a first TFT 110, storage capacitor Cs, second TFT 120, and EL element 170. The first TFT 110 is driven by a gate signal line 151 and functions as a switching element for capturing a data signal corresponding to a display information from a drain signal line 152. The storage capacitor Cs is connected to a source region 113s of the first TFT 110, for example, which is located on a side opposite from the drain signal line 152. A voltage corresponding to the data signal is applied to the storage capacitor Cs via the drain region 113d and the source region 113s. The storage capacitor Cs retains this voltage for a predetermined duration until the point when the TFT 110 is selected again and a new data signal is written. The second TFT 120 includes a gate 125 connected to the storage capacitor Cs (and to the first TFT 110 via the storage capacitor Cs), and serves to supply, from a drive signal line 153 to the organic EL element 170, a current corresponding to a voltage applied to the gate 125.
When the pixel area of every pixel region is equal, the layout of the components may be as shown in FIG. 1A. Based on this arrangement, a simple method for varying the areas (emissive regions) among the plurality of pixel regions arranged in a matrix may be to change the pixel region width in the horizontal direction for each color component, as shown in FIG. 1B for example. When varying the area of the pixel region for each color component in this manner, it is unnecessary to change the connection relationship between the signal lines and the first TFT 110. Accordingly, the relative position between the first TFT 110 and the gate and drain signal lines 151, 152 to which the first TFT 110 is connected need not be altered. Consequently, as shown in FIG. 1B, the size Ld (Lnd, LGd, LRd) of the drain region 113d of the first TFT 110 connected to the drain signal line 152 remains identical in each of the pixel regions correlated to R, G, and B. In contrast, the distance Ls (plan view distance projected onto the display plane surface) from the source region 113s, which is located on one side of a channel region 113c opposite from the drain region 113d, to the storage capacitor Cs (the region where the storage capacitor electrode 55 and the capacitor electrode line 54 overlap) connected to the source region 113s is varied between the pixel regions correlated to different color components.
When the distance Ls (LBs, LGs, LRs) is varied, differences result in the load LOs generated between the first TFT 110 and the storage capacitor Cs among the respective pixel regions. Consequently, the length of time during which a signal from the drain signal line 152 is written into the storage capacitor Cs and the gate of the second TFT 120 via the first TFT 110 becomes different for each color component, and uniformity is not attained. When using this configuration, because an EL element has a high emissive sensitivity with respect to a supplied current, variances in emissive luminance level among the pixel regions may likely result unless the device drive is controlled taking into consideration such differences in the conditions for writing into the second TFT 120. Further, because a pixel region having a larger width compared to those for other color components includes extra space, it may be devised to enlarge the storage capacitor Cs into the extra space to enhance memory performance. However, such a structure serves to actively vary the size of the storage capacitor Cs, namely, the charge accumulation capacity, in the respective pixel regions corresponding to different color components. Differences in the conditions for writing a data signal into the storage capacitor Cs via the first TFT thereby become larger among the pixel regions. As a result, adjustments and individual control for optimization in accordance with each color component becomes necessary, leading to not only an increase in design workload but also variances in adjustments and control. Such variances may lead to degradation in the uniformity of display (emissive luminance).